PCIe 2.0： 5GT/s 4Gb/s 500MB/s
PCIe 3.0： 8GT/s 8Gb/s 1GB/s
2017年5月7日 星期日
2017年4月16日 星期日
NVMe : Command flow
以下是發送一個NVMe admin/Io command 的流程。相關driver source code 可參考NVMe official website
1. Host Adds a command in the submission queue's tail entry
2. Host rings the submission queue's Tail Doorbell
3. Device fetch the command
4. Device process the command (done)
5. Device adds the completion result in the completion queue's tail entry (Completion result has its relevant command id)
6. Device send a Interrupt(Probably MSI-X)
7. Host reads the completion queue
7.1 Host has received the completion command
8. Host rings the completion queue's Head Doorbell
1. Host Adds a command in the submission queue's tail entry
2. Host rings the submission queue's Tail Doorbell
3. Device fetch the command
4. Device process the command (done)
5. Device adds the completion result in the completion queue's tail entry (Completion result has its relevant command id)
6. Device send a Interrupt(Probably MSI-X)
7. Host reads the completion queue
7.1 Host has received the completion command
8. Host rings the completion queue's Head Doorbell
NVMe : Queue Size / Queue entry Size
Queue 相關 size 的 configuration
- Admin Queue
- Completion Queue 和 Submission Queue 各只有一組
- Initial 時需設定Queue Size, 即AQA.ACQS, AQA.ASQS, controller 應support 2~4096個entry
- I/O Queue
- Initial 時需設定每個entry的Size, 即 CC.IOSQES = 6 (64 Byte), CC.IOCQES = 4 (16 Byte), 這是NVM command的size。
- 透過 CAP.MQES (Maximum Queue Entries Supported)得到 I/O Submission/Completion Queue support 的最大entry數量(最少兩個entry)。 在使用Admin Command Create I/O Queue時不要超過他
- 透過 Set Feature (Feature Id 07h) 設定host driver所需的Submission/Completion Queues數量 (最大64K個), 從completion queue 回來的資料可以得到Controller 所能allocate 的Submission/Completion Queue數量
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