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2014年5月29日 星期四

makefile example in windows

path
|
+--scr
|   +--a.txt
|   +--b.txt
|
+--dest


@IF EXIST "src" (
@ECHO src exist
)

REM set current path to variable
@set current=%cd%
@cd %current%/src

REM Don't show command in screen by add @
@

REM Show something
@ECHO Show Something..

REM Copy a a.txt from src folder to dest folder
cp src/a.txt dest

REM Copy all files from src folder to dest
cp -r src/* dest

REM Jum To Tag
@GOTO EXIT
:EXIT

REM create a new folder
mkdir NewFolder

2014年5月26日 星期一

PCI 相關spec 隨手紀錄 (To Be Continued)

# Type 0 PCI header register介紹
讀外插PCI controller的option Rom需先enable option rom access(ERBAR.bit0=1)
=>先將Expansion Rom BAR bit0設為1再access Expansion Rom BAR address(option rom address)

Bios階段enable MMIO access(command.bit1=1), enable IO access(command.bit0=1) 以及打開Bus Master(command.bit2=1)讓device可以主動發出memory cycle

# Configuration Space accessing

1. 如果是寫DOS的程式,透過 Int 1A 可以 access 超過 0xff 這個範圍

2. CF8, CFC方法: (發 IO transaction)
Read 就是Write address to 0xCF8, Read Dword data from 0xCFC 
Write 就是Write address to 0xCF8, Write Dword data to 0xCFC 



+  // 示範Read, Author: Martin Lee
+  DWORD ReadPci( CFG_ADDRESS  addr)
+  {
+      DWORD val;
+      DWORD daddr = addr.all | BIT(31);
+      WORD  oport = 0xcf8;
+      WORD  iport = 0xcfc;
+      
+      __asm{
+      mov eax, daddr
+      mov  dx, oport
+      out  dx, eax
+      mov  dx, iport
+      in  eax, dx
+      mov DWORD ptr val, eax
+      }
+      return val;
+  }

3. 直接MMIO accessing: (發 Memory transaction)
這個方法必須找到MMIO base address(x86通常都會在E000_0000H,這個位址沒有絕對要看chipset的romsip決定)來算出真正Bus/Device/Function/Register的位址,
                                                            
MMIO Address = MMIO_BASE_Addr + { bus number[27:20], device number[19:15], function number[14:12], extended register number[11:8], register number[7:2], offset [1:0] }.

#define PCIEX_BASE_ADDRESS   0xe0000000 
#define PCIE_CFG_ADDR(bus, dev, func, reg) \
((UINTN)(PCIEX_BASE_ADDRESS + ((bus) << 20) + ((dev) << 15) + ((func) << 12) + (reg) ))

# About PCI to PCI bridge:





2014年5月24日 星期六

SATA Power Management

SATA PHY有四種state, 需要注意回到PHYRDY的時間有沒有follow spec
  1. PHYRDY
  2. Partial:  <10us
  3. Slumber: <10ms
  4. DevSleep: <20ms
發動的時機有兩種: HIPM / DIPM,一個是Host主動發起,一個是device主動發。

想知道這個碟機有support什麼樣的power management能力可以看Identify table

 Word 76, bit 9: Support HIPM
 Word 76, bit 14: Support Device auto slumber
 Word 78, bit 3: Support DIPM
 Word 78, bit 8: Support DEVSLP
 Word 79, bit 3: Enable DIPM
 Word 79, bit 8: Enable DEVSLP

以下是控制AHCI controller來做HIPM/DIPM實驗:

HIPM:

  Partial:
  • PxCMD &= (~CMD_ASP) //mute bit 27
  • PxCMD |= CMD_ALPE //set bit 26
  • PxSCTL.IPM =0 // mute bit 11~8

 Slumber:
  • PxCMD |= CMD_ALPE | CMD_ASP //set bit 26 & bit 27
  • PxSCTL.IPM =0 // mute bit 11~8

發個ATA command來trigger, 然後Check PxSSTS.IPM 就知道有沒有成功


DIPM:

 發ATA command(Set Feature, EFh) 開啟碟機這項功能