APIC (Advanced Programmable Interrupt Controller)

APIC (Advanced Programmable Interrupt Controller)有分Local / IO APIC這兩種，這兩種都會同時存在系統上,一個管外部一個管內部。Local APIC是每個CPU核心都有的，而IO APIC(Intel 82093)是外部接收中斷的中斷控制器,可以決定要以什麼型態以及發給哪個核心。

Local APIC可以處理以下的中斷：

1. CPU Core相連的I/O設備。比如直接連在LINT0,LINT1 pin上的設備。

2. 外部的I/O設備。這些設備産生的中斷先經過I/O APIC,然後再通過LOCAL APIC到達處理器。

3. Inter-processor interrupts (IPIs), CPU核心之間的中斷。當一個核心想中斷另外一個就可以用IPI。



4. APIC定時器中斷。APIC內部的定時器

5. Performance monitoring counter interrupts，

6. Thermal Sensor Interrupt

7. APIC內部錯誤中斷。

何謂local vector table (LVT): It allows software to specify the manner in which the local interrupts are delivered to the processor core.(在APIC內部)

APIC在所佔用的MMIO address:

APIC和8259的連接方式:



APIC在CPU內的的連接方式:連接方式會因為各種不同CPU等級而用System bus (for Xeon) 或 3-wired APIC bus (for P6):



IOAPIC

IOREDTBL (IO Redirection Table)

There are 24 I/O Redirection Table entry registers. Each register is a dedicated entry for each interrupt input signal.

Following there are two 32-bit register for each IRQ. The first IRQ has indexes 0x10 and 0x11, the second 0x12 and 0x13, the third 0x14 and 0x15, and so on. So the Redirection Entry register for IRQ n is 0x10 + n * 2 (+ 1). 透過對應公式可以找到IRQn 所對應的 RTE(Redirection Table Entry),有了RTE就可以找到Vector來送給某個CPU的Local APIC。 In the first of the two registers you access to the LOW uint32_t / bits 31:0, and the second for the high uint32_t / 63:32. Each redirection entry is made of the following fields:

Field	Bits	Description
Vector	0 - 7	The Interrupt vector that will be raised on the specified CPU(s).
Delivery Mode	8 - 10	How the interrupt will be sent to the CPU(s). It can be 000 (Fixed), 001 (Lowest Priority), 010 (SMI), 100 (NMI), 101 (INIT) and 111 (ExtINT). Most of the cases you want Fixed mode, or Lowest Priority if you don't want to suspend a high priority task on some important Processor/Core/Thread.
Destination Mode	11	Specify how the Destination field shall be interpreted. 0: Physical Destination, 1: Logical Destination
Delivery Status	12	If 0, the IRQ is just relaxed and waiting for something to happen (or it has fired and already processed by Local APIC(s)). If 1, it means that the IRQ has been sent to the Local APICs but it's still waiting to be delivered.
Pin Polarity	13	0: Active high, 1: Active low. For ISA IRQs assume Active High unless otherwise specified in Interrupt Source Override descriptors of the MADT or in the MP Tables.
Remote IRR	14	TODO
Trigger Mode	15	0: Edge, 1: Level. For ISA IRQs assume Edge unless otherwise specified in Interrupt Source Override descriptors of the MADT or in the MP Tables.
Mask	16	Just like in the old PIC, you can temporary disable this IRQ by setting this bit, and reenable it by clearing the bit.
Destination	56 - 63	This field is interpreted according to the Destination Format bit. If Physical destination is choosen, then this field is limited to bits 56 - 59 (only 16 CPUs addressable). You put here the APIC ID of the CPU that you want to receive the interrupt. TODO: Logical destination format...

Vector送到CPU後， CPU會到Physical memory上查IDT(Interrupt Descriptor Table)，找到ISR並執行

上圖說明IDT。 在Protect Mode + APIC mode的架構, Interrupt Vector對應的ISR位址表叫 IDT。 對比早期的架構 ( Real Mode + PIC mode), Interrupt Vector 對應的ISR叫做 IVT, 其實都是用來說明 where the Interrupt Service Routines (ISR) are located

參考資料；http://wiki.osdev.org/IOAPIC
參考資料；http://rock3.info/blog/tag/idt/