x86 spec / Bios 常見術語

[ CPUID ] 

CPUID 是 80486 CPU 新增的一個指令，它的用途在於鑑別 CPU 種類或提供 CPU 特性，讀取方式如下:

void cpuid (DWORD  idx) // idx是index, 不同index得到不同資料 {     _asm     {         mov eax, idx         cpuid          }     // eax, edx, ecx,...值為CPU相關的資訊 }

列出部分的資訊:

EAX=0: Highest Function Parameter
EAX=0: Get vendor ID
EAX=1: Processor Info and Feature Bits
EAX=2: Cache and TLB Descriptor information
EAX=3: Processor Serial Number
EAX=4 and EAX=Bh: Intel thread/core and cache topology
EAX=7, ECX=0: Extended Features
EAX=80000000h: Get Highest Extended Function Supported
EAX=80000001h: Extended Processor Info and Feature Bits
EAX=80000002h,80000003h,80000004h: Processor Brand String
EAX=80000005h: L1 Cache and TLB Identifiers
EAX=80000006h: Extended L2 Cache Features
EAX=80000007h: Advanced Power Management Information
EAX=80000008h: Virtual and Physical address Sizes

[  Memory remapping ]
64位元OS將system view的TOM(Top Of Memory)之上的memory定位到DRAM的MMIO缺口

[ Romsip ]

BIOS image 中會包一些 額外的bytes(binary)，用在power-on時 configure NB/SB的 registers

[ Frame buffer ]
顯示卡註冊的一塊連續memory

[ UMA ] (Unified Memory Architecture)
A computer that has graphics chips built into the motherboard that use part of the computer's main memory for video memory is said to have Unified Memory Architecture. (內顯用的記憶體)

[ UMA ] (Upper Memory Area)
早期16位元CPU所定義的一塊記憶體。也就是640KB(A000:0)以上384KB的memory，這部分有一些是設定成shadow memory(ROM), 有些是RAM

[ shadow registers/shadow memory ]  
透過設定可以讓程式access的register/memory，實際上由shadow register/memory來回應

[ PAM ]
Programmable Attribute Map (PAM(BIOS))位於 768k至1M之間的memory(UMA).
PAM is a legacy BIOS ROM area in MMIO. It is overlaid with DRAM used as a faster ROM storage area.

[ A~F Segment ]
早期16位元所定義的記憶體(UMA)內, 每個segment 為64KB, 共有6個 (A_0000h, B_000h,...,F_000h) total 384KB

[ MTRR ]
MTRR (Memory type range registers) 是CPU內的MSR,用來告訴CPU要如何最佳的存取各個記憶體區段，也就是說CPU要以哪種快取模式來進行存取。

[ Snoop & non-snoop ]
Snooping is part of cache coherency protocol implementations. If cache coherency is not required for correctly functioning application/driver one can issue non-snooped transactions that don't snoop (potentially more recent) copies of data in caches but directly read/writes memory.

[ TOLM ]
Top of Low Memory Register: This register contains the maximum address below 4GB that should be treated as a memory access, and is defined on a 128-MB boundary (Intel Memory controller hub spec)

[ TSEG ]
This is a protected memory space (typically) located in OS memory. It can only be accessed by code in SMMode, just as Cseg (C_000h) is. Unlike Cseg, the address is configurable, defined by the core, and access is enforced by core SMRRs. .

[ Control registers ]
(CR0, CR1, CR2, CR3, and CR4) determine operating mode of the processor and the characteristics of the currently executing task. it is also a MSR. (By manipulating CR0, CPU can switch between protect mode and real mode)

[A20 Line/Gate]
The A20 Address Line is the physical representation of the 21st bit. To remain compatible with the 8086, a quirk in the 8086 architecture (memory wraparound) had to be duplicated in the AT. To achieve this, the A20 line on the address bus was disabled by default.(有些古老的DOS軟體會用wraparound, 為了相容性, default disable A20 )
開關A20有兩種方法:
1.  enables/disables A20 using INT 15h AX=2401h(enable) / 2400h(disable)
2.  直接操作IO
+  val = inportb(0x92);
+  outportb (0x92, val  |  BIT1) //enable
+  outportb (0x92, val  & ~BIT1) //disable

[ BSP ]
bootstrap processor(core). The BSP executes the BIOS’s boot-strap code to configure the APIC environment, sets up system-wide data structures, and starts and initializes the APs. When the BSP and APs are initialized, the BSP then begins executing the operating-system initialization code.

[ AP ]
application processor(core). A processor that is not the BSP. All APs are in a halted state when the BIOS first gives control to the operating system.

PS. 由於Bios不支援multi-thread(SW/HW), 硬體選擇 BSP 來 power-on, 接著 BSP會 configure AP(如configure 每個AP的APIC)，之後 AP 會被停掉(halt)只剩BSP, 直到 OS接手, AP 才會被喚醒

[ SMP ]
symmetric multiprocessing. Using multiple processors which share the same physical memory in the same computer at the time.

[ CPU Cores ]
Independent processing units, 包含自己的uncore(APIC, INTC, MSR,...)

[ Processor die ]
It is a single continuous piece of semiconductor material (usually silicon). A die can contain any number of cores. Up to 15 are available on the Intel product line. Processor die is where the transistors making up the CPU actually reside.

[ Cluster ]
就我認知，可以看成是chip裡的一個模組，這個模組將一堆Core結合在一起成立獨立的運算群組, cluster實現方法為NUMA

[ NUMA ]
NUMA (non-uniform memory access) is a method of configuring a cluster of microprocessor in a multiprocessing system so that they can share memory locally, improving performance and the ability of the system to be expanded. NUMA is used in a symmetric multiprocessing ( SMP ) system.

[ LLC ]
LCC (Last Level Cache): Intel 在 Cache 上對於所有處理器所做的設計，LLC 就是 shared L3 快取，不同於 L1、L2 為各core獨有無法共用，LLC 各核心都可共享，因此加速各核心之間的溝通(共享的結構)，各部份可單獨存取，也可以不同核心存取同一份資料，減低到Memory撈資料延遲問題。

[ SAD/TAD ] 

Source Address Decoding / Target address decoding, 當平台有多個CPU/MCH時Memory分配設定方法。請參考這篇(About SAD/TAD (in Intel Xeon) with some background memory knowledge)

[DualBIOS]
主機板上兩顆實體BIOS (Main BIOS/Backup BIOS), 正常的狀態下由Main BIOS開機，若Main BIOS損毀時則由Backup BIOS開機並將Bios複製到Main BIOS


(持續更新)